This invention relates generally to processing within a computing environment, and more particularly to dynamic mode transitions for cache instructions.
In computers, a cache is a component that improves performance by transparently storing data such that future requests for that data can be served faster. The data that is stored within a cache might be values that have been computed earlier or duplicates of original values that are stored elsewhere (e.g. main memory). If requested data is contained in the cache (cache hit), this request can be served by simply reading the cache, which is comparably faster. Otherwise (cache miss), the data has to be recomputed or fetched from its original storage location, which is comparably slower.
Cache operations in a shared cache may be performed by accessing a shared pipeline. A pipeline may be considered as a set of data processing elements connected in series, so that the output of one element is the input of the next one. An instruction pipeline may be used in a computing device to increase instruction throughput (the number of instructions that can be executed in a unit of time). The fundamental idea is to split the processing of a computer instruction into a series of independent steps, with storage at the end of each step. This allows the computer's control circuitry to issue instructions at the processing rate of the slowest step, which is much faster than the time needed to perform all steps at once. The term pipeline refers to the fact that each step is carrying data at once (like water), and each step is connected to the next (like the links of a pipe.)
To maximize the performance of a cache, requests accessing a shared cache pipeline will speculatively access the data from the cache when performing other steps of the operation, such as sending coherency updates to lower levels of the cache. This allows the request to quickly return cache data for cases where the coherency updates are unnecessary.